Post-CMP models capture such effects as dishing and erosion after the CMP process is complete. However, building a physics-based chip-scale model for the post-deposition profile height is still a challenge, due to the complex nature of the multi-stage process.
With modern equipment, it is possible to get high-quality AFM or high resolution profiler (HRP) 2D and 1D scans for post-deposition (pre-CMP) profiles. Flowable CVD (FCVD), high aspect ratio process (HARP), and enhanced HARP (eHARP) deposition significantly improves the gap-filling capability, which results in denser films with void-free gap-fill-in features with an aspect ratio of 10:1 and more. One challenge of building an accurate and complete CMP modeling process is the generation of a pre-CMP profile before polishing.Īt 20nm technology and below, gap filling with high-density plasma chemical vapor deposition (HDP-CVD) becomes increasingly challenging, so new deposition technologies have emerged and become standard. It also includes deposition models for pre-CMP profile generation. These measured data are an important part of the model-building process because CMP modeling doesn‘t consist entirely of polishing models. Measurements include atomic force microscope (AFM) or other profiler tool scans, and transmission electron microscopy (TEM) or scanning electron microscopy (SEM) cross-section images. The next step in CMP modeling is collecting data from the test wafers. Cross section view of Al RMG technology: (a) Polysilicon patterning (b) Oxide deposition and POP (c) Poly removal, Al deposition, and polishing. Figure 2 illustrates both of these steps.įigure 2. In Al RMG technology, the sacrificial polysilicon (poly) layer is removed, and the Al layer is deposited instead, then polished.
For POP modeling, an inverse (or negative) of the poly layer is used for oxide deposition and polishing, while a positive poly layer is used for the Al RMG step. Due to the specific nature of HKMG and Al RMG technology, test chip patterns of POP and Al RMG are correlated. These different combinations of rectangle sizes and the spaces between them allow a wide variety of density, width, and space combinations for the test patterns. In place of trenches, we created special test patterns for the STI, POP, and Al RMG CMP steps consisting of regular patterns of similarly-oriented rectangles separated by a variety of spacing values in both the horizontal and vertical directions. Restrictive design rules introduced at the 20nm technology node help improve layout unifomity, but make it impossible to use long parallel trenches in array blocks for FEOL CMP. Test chips play a critical role in in the development of accurate CMP modeling, so the first steps in building any new CMP model are to design test patterns and manufacture the test wafers. Let’s take a look at just what it takes to build an effective FEOL CMP model. The increasingly high cost of lithography due to multi-patterning, combined with more demanding depth of focus (DOF) requirements and the increased criticality of the HKMG CMP steps, have expanded interest in FEOL CMP modeling at advanced nodes. At 20nm and below, these two CMP steps are especially critical in forming the gates of transistors, because variation in gate height of just a few atomic layers leads to measurable transistor performance variability. When gate-last high-k metal gate (HKMG) technology was introduced at the 45nm technology node, two new CMP steps were introduced in the front end of line (FEOL) process flow- poly open planarization (POP) and replacement metal gate (RMG). For example, at 20nm, multi-patterning requirements created a whole new set of design constraints to enable successful double-pattterning manufacturing. However, critical dimensions of integrated circuits (IC) continuously shrink for each new technology node, imposing more demanding requirements on wafer planarity and depth of focus (DOF) limits.
Currently, CMP modeling is widely used for hotspot detection in shallow trench isolation (STI) and back end of line (BEOL) layers as part of a design for manufacturing (DFM) flow (Figure 1).įigure 1. CMP modeling allows design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a wafer. By providing superior imaging and cross-sectional analysis, as well as a correlated workflow using artificial intelligence (AI), ZEISS delivers new insights from macroscale to nanoscale with fast time to results.By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeidįor decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. ZEISS solutions achieve significant advancements for package failure analysis workflows.
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